December 11, 2017
Comments Off on Design of a Power Optimal Reversible FIR Filter for Speech Signal Processing
Posted in: IEEE 2017, VLSI
Design of a Power Optimal Reversible FIR Filter for Speech Signal Processing Abstract: In this paper, an efficient architecture of FIR filter structure is presented. For achieving low power, reversible logic mode of operation is implemented in the design. Area overhead is the tradeoff in the proposed design. From the synthesis results, the proposed low power […]
December 11, 2017
Comments Off on Design of a Compact Reversible Carry Look Ahead Adder Using Dynamic Programming
Posted in: IEEE 2017, VLSI
Design of a Compact Reversible Carry Look-Ahead Adder Using Dynamic Programming Abstract: This paper presents a new method for designing a reversible carry look-ahead adder (RCLA) based on dynamic programming. In this method, we propose a faster technique for generating carry output, which also outperforms the existing ones in terms of number of operations. In […]