December 11, 2017
Comments Off on Design of Full Adder circuit using Double Gate MOSFET
Posted in: IEEE 2017, VLSI
Design of Full Adder circuit using Double Gate MOSFET Abstract: This paper presents a design of a one bit full adder cell based on degenerate pass transistor logic (PTL) using Double Gate MOSFET. The design cell is degenerate 5-T XOR-XNOR module. This design has been compared with existing one-bit full adder cell based on degenerate […]
December 11, 2017
Comments Off on Design of Adiabatic Dynamic Differential Logic for DPA Resistant Secure Integrated Circuits
Posted in: IEEE 2017, VLSI
Design of Adiabatic Dynamic Differential Logic for DPA-Resistant Secure Integrated Circuits Abstract: Production of cost-effective secure integrated chips, such as smart cards, requires hardware designers to consider tradeoffs in size, security, and power consumption. To design successful security-centric designs, the low-level hardware must contain built-in protection mechanisms to supplement cryptographic algorithms, such as advanced encryption standard […]