December 11, 2017
Comments Off on Design of Optimized Reversible Binary and BCD Adders
Posted in: IEEE 2017, VLSI
Design of Optimized Reversible Binary and BCD Adders Abstract: Reversible logic has emerged as a possible low cost alternative to conventional logic in terms of speed, power consumption and computing capability. An adder block is a very basic and essential component for any processor and optimized design of these adders’ results in efficient processors. In this […]
December 11, 2017
Comments Off on Design of Low Power and High Speed Carry Select Adder using Brent Kung adder
Posted in: IEEE 2017, VLSI
Design of Low Power and High Speed Carry Select Adder using Brent Kung adder Abstract: In this paper, Carry Select Adder (CSA) architectures are proposed using parallel prefix adders. Instead of using dual Ripple Carry Adders (RCA), parallel prefix adder i.e., Brent Kung (BK) adder is used to design Regular Linear CSA. Adders are the […]