December 11, 2017
Comments Off on Energy and Area Efficient ThreeInput XOR XNORs With Systametic Cell Design Methodology
Posted in: IEEE 2017, VLSI
Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology Abstract: In this brief, we propose three efficient three-input XOR/XNOR circuits as the most significant blocks of digital systems with a new systematic cell design methodology (SCDM) in hybrid-CMOS logic style. SCDM, which is an extension of CDM, plays the essential role in designing efficient […]
December 11, 2017
Comments Off on Design of Priority Encoding Based Reversible Comparators
Posted in: IEEE 2017, VLSI
Design of Priority Encoding Based Reversible Comparators Abstract: Reversible logic has emerged as an alternate design technique to the conventional logic, resulting in lower power consumption and lesser circuit area. Comparators are a key element in most digital systems. In this paper we propose two new reversible comparator designs based on the concept of priority […]