December 11, 2017
Comments Off on Design of Register File using Reversible Logic
Posted in: IEEE 2017, VLSI
Design of Register File using Reversible Logic Abstract: Register file is the paramount aspect in computer memory unit. Eight bits (one memory unit) results in a single register and 32 of such register make up a register file. In this paper w e have presented the design of a complete register file using reversible logic […]
December 11, 2017
Comments Off on Quality-Aware Sub graph Matching over Inconsistent Probabilistic Graph Databases
Posted in: IEEE 2017, Java
Quality-Aware Sub graph Matching over Inconsistent Probabilistic Graph Databases Abstract Resource Description Framework (RDF) has been widely used in the Semantic Web to describe resources and their relationships. The RDF graph is one of the most commonly used representations for RDF data. However, in many real applications such as the data extraction/integration, RDF graphsintegrated from different data sources […]