December 11, 2017
Comments Off on Low Power High Speed Area Efficient Error Tolerant Adder Using Gate Diffusion Input Method
Posted in: IEEE 2017, VLSI
Low Power High Speed Area Efficient Error Tolerant Adder Using Gate Diffusion Input Method Abstract: In digital VLSI circuits, perfectly accurate outputs are not always needed. So designers have started to design error tolerance circuits which provide good enough output for computation. On the basis of this fact, error tolerant adder (ETA) is designed which […]
December 11, 2017
Comments Off on Logic Synthesis in Reversible PLA
Posted in: IEEE 2017, VLSI
Logic Synthesis in Reversible PLA Abstract: Reversible logic have been motivated by consideration of zero-energy computation. Re-configurability and structural regularity of Programmable Logic Devices caused wide use of it by the logic designers. In this paper, we propose a design algorithm for a PLA (Programmable Logic Array) with a newly designed low cost 3 × […]