December 11, 2017
Comments Off on Low Power Reconfigurable Hilbert Transformer Design with Row Bypassing Multiplier on FPGA
Posted in: IEEE 2017, VLSI
Low Power Reconfigurable Hilbert Transformer Design with Row Bypassing Multiplier on FPGA Abstract: Reconfigurability and low power have always been the main concern for the efficient filter implementation. This paper introduces two new low power and high speed reconfigurable Hilbert transformer designs. These designs are based on the carry save adder (CSA) and ripple carry adder […]
December 11, 2017
Comments Off on Low Power Multiplier Architectures Using Vedic Mathematics in 45nm Technology for High Speed Computing
Posted in: IEEE 2017, VLSI
Low Power Multiplier Architectures Using Vedic Mathematics in 45nm Technology for High Speed Computing Abstract: Speed and the overall performance of any digital signal processor are largely determined by the efficiency of the multiplier units present within. The use of Vedic mathematics has resulted in significant improvement in the performance of multiplier architectures used for […]