December 11, 2017
Comments Off on Design Methodology for Voltage-Scaled Clock Distribution Networks
Posted in: IEEE 2017, VLSI
Design Methodology for Voltage-Scaled Clock Distribution Networks Abstract: A low-voltage/swing clocking methodology is developed through both circuit and algorithmic innovations. The primary objective is to significantly reduce the power consumed by the clock network while maintaining the circuit performance the same. The methodology consists of two primary components: a novel D-flip-flop (DFF) cell that maximizes […]
December 11, 2017
Comments Off on Analysis and Mapping for Thermal and Energy Efficiency of 3-D Video Processing on 3- D Multicore Processors
Posted in: IEEE 2017, VLSI
Analysis and Mapping for Thermal and Energy Efficiency of 3-D Video Processing on 3-D Multicore Processors Abstract: Three-dimensional video processing has high computation requirements and multicore processors realized in 3-D integrated circuits (ICs) provide promising high performance computing platforms. However, the conventional approaches to accelerate the computations involved in 3-D video processing do not exploit […]