December 11, 2017
Comments Off on A Calibration Technique for Bang-Bang ADPLLs Using Jitter Distribution Monitoring
Posted in: IEEE 2017, VLSI
A Calibration Technique for Bang-Bang ADPLLs Using Jitter Distribution Monitoring Abstract This brief presents a built-in self-calibration (BISC) technique for minimization of the total jitter in bang-bang all-digital phase-locked loops (ADPLLs). It is based on the addition of a monitoring phase-frequency detector (PFD) with tunable delay cells for the reference clock and the divider clock and a counter for this PFD output signal. This […]
December 11, 2017
Comments Off on A 28-nm CMOS 1 V 3.5 GSs 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme
Posted in: IEEE 2017, VLSI
A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With Signal-Independent Delta-I Noise DfT Scheme Abstract This paper presents a 3.5 GS/s 6-bit current-steering digital-to-analog converter (DAC) with auxiliary circuitry to assist testing in a 1 V digital 28-nm CMOS process. The DAC uses only thin-oxide transistors and occupies 0.035 mm2, making it suitable to embedding in VLSI systems, e.g., field-programmable gate array (FPGA). To cope with […]