December 11, 2017
Comments Off on Utilization-Aware Self-Tuning Design for TLC Flash Storage Devices
Posted in: IEEE 2017, VLSI
Utilization-Aware Self-Tuning Design for TLC Flash Storage Devices Abstract The high-density, low-cost triple-level-cell (TLC) flash memory has gradually dominated the flashstorage market because of the fast-growing demand for storage capacity. However, the advances of manufacturing technologies also make TLC flash memory suffer serious performance degradation compared with the low-density, high-performance single-level-cell (SLC) flash memory. To address this issue, some vendors enable blocks of TLC flash memory to work as […]
December 11, 2017
Comments Off on Optimum pMOS-to-nMOS Width Ratio for Efficient Subthreshold CMOS Circuits
Posted in: IEEE 2017, VLSI
Optimum pMOS-to-nMOS Width Ratio for Efficient Subthreshold CMOS Circuits Abstract The subthreshold region of operation in digital CMOS circuits provides a suitable low-power solution for many applications that need tremendously low-energy operation. However, this advantage comes at the cost of speed, so enhancing the speed of subthreshold circuits can expand their application spectrum. This paper presents the optimum pMOS-to-nMOS width ratio that leads to the maximum frequency of operation in […]