December 11, 2017
Comments Off on Multiplier less Unity-Gain SDF FFTs
Posted in: IEEE 2017, VLSI
Multiplier less Unity-Gain SDF FFTs Abstract: In this brief, we propose a novel approach to implement multiplierless unity-gain single-delay feedback fast Fourier transforms (FFTs). Previous methods achieve unity-gain FFTs by using either complex multipliers or nonunity-gain rotators with additional scaling compensation. Conversely, this brief proposes unity-gain FFTs without compensation circuits, even when using nonunity-gain rotators. […]
December 11, 2017
Comments Off on A 1-16-Gbs All-Digital Clock and Data Recovery With a Wideband, High-Linearity Phase Interpolator
Posted in: IEEE 2017, VLSI
A 1-16-Gb/s All-Digital Clock and Data Recovery With a Wideband, High-Linearity Phase Interpolator Abstract: An all-digital phase interpolator (PI)-based clock and data recovery (CDR) is proposed in this paper to accommodate any data rate continuously from 1 to 16 Gb/s with quadrature sampling clocks from 4 to 8 GHz. A new, low-power and two-step PI […]