A 1-16-Gbs All-Digital Clock and Data Recovery With a Wideband, High-Linearity Phase Interpolator

A 1-16-Gb/s All-Digital Clock and Data Recovery With a Wideband, High-Linearity Phase Interpolator

Abstract:

An all-digital phase interpolator (PI)-based clock and data recovery (CDR) is proposed in this paper to accommodate any data rate continuously from 1 to 16 Gb/s with quadrature sampling clocks from 4 to 8 GHz. A new, low-power and two-step PI with high linearity over 4-8 GHz range is presented. The all-digital CDR control loop adopts a multimode phase detection scheme, which enables continuous data rate support. The digital architecture not only eliminates the large filtering capacitor, but also makes the design more tolerant to process, voltage, and temperature variations. The CDR core occupies 0.088 mm² in a commercial 65-nm CMOS technology and consumes 73.1 mA at 16 Gb/s from a 1.2 V power supply. The differential nonlinearity of the PI is measured to be within 0.48 LSB. Measurement results show that this CDR can function at the proposed phase detection modes and is able to exceed the SONET OC-192 jitter tolerance mask at least by 0.2 UI at high frequencies (4-100 MHz), with 2³¹ – 1 pseudorandom binary sequence data pattern at 10 Gb/s and a target bit error rate of 10⁻¹².

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